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Data Compression

JPEG Encoder

Block diagram Image: DLR RM-OS

The JPEG Encoder (JE) is a high-performance, stand alone image compression IP core. It is fully compliant with the baseline ISO/IEC 10918-1 standard. The current version is functional in the single colour mode. 8-bit and 12-bit JE cores are implemented on different FPGA devices.

Features

• Baseline ISO/IEC 10918-1 standard compliant
• Programmable Quantization Tables
• Programmable DC / AC Huffman Tables
• Supports any image size. (The maximum image line width is limited by the number of block RAMs inside a specific ASIC or FPGA device)
• No external memory is required
• Fully-synchronous design with a single external clock
• Automatic marker generation